无线电工程

针对在FPGA内部产生高速m序列时,处理时钟频率远低于数据生成速率的问题,采用延迟法、等效法和代换法3种方式,设计了并行m序列产生的并行结构,并在FPGA上进行了实现。经过测试,生成的并行m序列完全符合标准格式要求。这种并行结构在高速通信系统中的加解扰、误码测试和编译码测试等环节取得了较好的应用效果。

To resolve the problem of processing clock frequency far below data generation rate in generating high-speed m sequence in FPGA,this paper adopts three methods of delay method,equivalent method and substitution method to design the parallel structure for generating paralleling m sequence and implements it on FPGA. The test results show that the generated paralleling m sequences fully meet the standard format requirements. This parallel structure achieves better application effects in the tests of scrambling and descrambling,BER,and coding and decoding in high-speed communication system.