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设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的紧凑型1024点流水线架构快速傅里叶变换(Fast Fourier Transform, FFT)处理器。采用基-25 FFT算法用于减少旋转因子复数乘法运算的复杂度,硬件实现上采用了单路延迟负反馈(Single Delay Feedback, SDF)流水线架构。提出了旋转因子拆分方案,将旋转因子W■拆分为W■和W■,使得所有的复数乘法运算全部由正则有符号数(Canonical Signed Digit, CSD)常数乘法器来完成,无需任何只读存储器(Read Only Memory, ROM)对旋转因子常数值进行存储,大幅降低了设计所消耗的硬件成本。评估结果显示,与以往的设计方案相比,所提方案至少节约逻辑单元使用量(Logic Elements, LEs) 28%,记忆体单元使用量(Memory bits, MBs) 48%。
Abstract：A compact 1024-point pipelined FFT processor based on FPGA is designed.Radix-25 FFT algorithm is adopted to reduce the calculation complexity of twiddle factors.The SDF pipelined architecture is used for hardware implementation.A scheme of twiddle factor partition is proposed, which divides twiddle factor Wi1024 into W11024 and Wi512.By doing this, all of the complex multiplications can be achieved by CSD constant multipliers.Furthermore, ROM for storing the constant values of twiddle factors can be removed, and as a result, the cost of hardware is significantly reduced.The evaluation result shows that the proposed scheme can reduce at least 28% LEs and 48% MBs as compared with previous schemes.
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基本信息:
DOI：
中图分类号:TP332;TN791
引用信息:
[1]于建,霍永华,焦利彬等.一种紧凑型1024点流水线FFT处理器设计[J].无线电工程,2021,51(11):1326-1334.
基金信息:
河北省自然科学基金项目(F2020101001); 河北省留学回国人员资助项目(C20210301); 河北省承德市科学技术研究与发展计划项目(202001B04); 河北民族师范学院科学技术研究项目(PT2019026)~~