无线电工程

通过对锁相环(PLL)与直接数字频率合成器(DDS)的工作原理分析,得出PLL相位噪声数学模型与减小DDS杂散的方法。介绍了一种S波段的宽带小步进频率合成器的设计与实现,并通过了实物制作与测试。测试在输出频率范围为1 800²350 MHz、频率步进为10 k Hz时,相位噪声为-88 d Bc/Hz@10 k Hz,杂散低于-60 d Bc。测试结果证明,该频率合成器的性能达到了设计指标要求。

By analyzing the theory of phase-locked loop( PLL) and direct digital synthesizer( DDS),the working model of phase lock loop noise and the method of lowering the spurious frequency of DDS are obtained. A design and implementation of S-band frequency synthesizer with broadband and fine resolution are introduced,which is produced and tested. Meanwhile,a design of 1 800 ²350 MHz frequency synthesizer with 10 k Hz step is realized. Through hardware test,the phase noise is-88 d Bc / Hz@ 10 k Hz and the spurious frequency is less than-60 d Bc. The test results show that this frequency synthesizer can meet the design requirements。